1. Field of the Invention
The invention relates to methods of using field programmable gate arrays (FPGA) and in particular to a method of including the operation of more than one integrated circuit within the array.
2. Description of the Prior Art
Of the many varieties of integrated circuits available on the market today, field programmable gate arrays (FPGAs) are particularly useful when building many kinds of electronic devices and systems. Because FPGAs allow the designer to integrate complex logic that is peculiar to his application in one or perhaps a few integrated circuits without suffering the cost, delay and risk that typically are incurred when designing a custom integrated circuit, use of FPGAs greatly reduce both design cost and time-to-market for new products.
Not withstanding the great utility of FPGAs, there exist several limitations to the usefulness of these devices. FPGAs consist of logic circuits and interconnects that are configured by yet additional configuration logic circuits distributed within the array. The result is that FPGA chips are large compared with custom designed logic chips of functionality similar to the FPGA logic implementation. The large size of FPGAs compared to custom logic chips increases their cost and power dissipation and reduces their operating speed owing to the greater on-chip wiring distances and resulting greater wiring capacitance.
A further limitation of FPGAs is their requirement for complex, expensive integrated circuit processes for reasonable implementation of moderate to large capacity FPGAs. In this context, complex integrated circuit processes are typically those offering many levels or layers of interconnection wiring on the chip. Such processes are necessary to efficient implementation of FPGAs due to the need to distribute configuration logic throughout the array, and because FPGAs are fundamentally used to implement random logic designs with the attendant topological complexity. In contrast to FPGAs, certain highly regular, single purpose integrated circuits achieve very much higher densities and performance from simpler, lower cost processes. An example of such circuits would be memory circuits, for instance. Memory circuits are typically built with processes having three or fewer layers of interconnect where as FPGAs frequently are built on processes using six or more layers of interconnect. The result is that while memory functions can be provided within a user's logic design when implemented on many FPGAs, this memory is quite costly compared to similar amounts of memory in the form of standard memory chips. Further, there is a rather small, upper limit to the. amount of memory that can be implemented on a single FPGA. For instance, The Xilinx Vertex II family of FPGAs offers up to 5.5 million bits of RAM whereas a Samsung MT6VI6M18F2-3M DRAM provides 288 million bits.
A particularly useful aspect of FPGAs is the ability of a logic designer using FPGAs to perform much of his design activity, including functional verification and timing validation, on FPGA design software. Use of the FPGA design software gives a great advantage compared to designing logic systems using many separate parts because the interconnect between parts of the FPGA is fully characterized within the design system and can therefore be validated. In contrast, the designer using multiple devices and designing a circuit board, for instance, to interconnect these parts cannot be sure of the propagation characteristics (time delay, waveform reflections and distortions, etc.) introduced by the circuit board. This, in turn introduces uncertainty in to the design process, and frequently requires design modifications, after the first unit(s) have been made, to correct the signal transmission effects introduced by the interconnecting circuit board.
An interesting aspect of FPGA technology is that the number of logic gates that may be implemented by a user on a single FPGA chip has increased dramatically over time. In 2001, gate arrays with a few million gates capacity were available commercially (e.g. Xilinx Vertex II, etc.). It is forecast that by 2004, FPGA parts capable of implementing up to 50 million gates of user specified logic will be commercially available. This has resulted in the very significant limitation that sufficient design talent and resources to generate new logic designs that can utilize these very large FPGAs is not easily available. Particularly, it has been noted that newly implemented FPGA designs tend to include ever increasing proportions of logic imported or copied from previous designs.
Specialized and more highly productive logic design tools are also being introduced that speed the design and design verification for new logic designs. Examples of these new design tools are the Handel-C and Pebble hardware design languages that convert relatively high level descriptions of an FPGA user's desired logic functionality into a detailed design. Particularly, useful is the Handel-C compiler approach which allows the user to define the desired functionality of his very high speed integrated circuit (VHSIC) in the form of an algorithm in C programming language. The Handel-C compiler then generates a VHSIC hardware description language (VHDL) description of a logic circuit that implements the functionality of the described algorithm. The FPGA design process then proceeds with the steps of 1) synthesis: conversion of the VHDL logic description into a specific logic topology implementable in FPGA gates; 2) place and route: assignment of FPGA gales to specific locations within the FPGA chip and assignment of specific interconnection paths within the FPGA to connect the logic signals; and 3) programming of the FPGA so that it will perform the user's desired functionality. These latter steps (1–3) are provided, typically, as part of existing FPGA design tools, with the Handel-C compiler being an “adjunct” functionality. Further, it is often desirable to review the arrangement and functional speed of the design as implemented in the FPGA by this design process. Simulation software is typically used for this process that relies on known processing delay for individual FPGA logic elements, and for various configurations of FPGA internal interconnects.
In particular this Handel-C compiler approach to logic design allows algorithms that currently operate on conventional computers to be used as the basis of logic designs with the advantage of capturing what is often proven and tested functionality for complex tasks. An example of such an algorithm-to-logic transformation would be the implementation of a transfer control protocol/internet protocol (TCP/IP) processing “stack” implemented in logic, but derived from a C program with this function.
Notwithstanding the very considerable efficiency of time and assurance of correct functionality that is afforded by the Handel-C and similar design methodologies, there is a significant limitation in the current art with respect to the unconstrained use of C programs as the basis for logic design. Particularly, it is generally difficult to implement complex data structures, pointer references and object oriented programs in gate arrays using the Handel-C programming technique. This limitation with respect to data structures and software objects is in part due to the rather limited amounts of memory elements available within FPGAs and also due to limitations of the programming languages currently available. Since very many interesting and useful functionalities have been implemented in programs that utilize complex data structures and/or employ object oriented programming techniques, which is not directly implementable using the current Handel-C design technique, FPGA implementation of these algorithms becomes very problematic and requires very great expenditure of design and design verification effort in many cases.
It is the object of the invention to allow the direct application of FPGAs to a wider set of user defined applications by better supporting large amounts of memory.
Another object of the invention is to provide FPGAs with more extensive memory, dedicated processor and similar functionality than is practical to do by embedding such functionality within the FPGA chip.
A yet further object of the invention is to realize electronic modules containing one or more FPGAs together with supporting circuits such as memory, processors, communications interface circuits and the like; that are fully characterized with respect to functionality and performance to an extent allowing the entire module to be treated as an FPGA component for purposes of generating, documenting and validating a user design with standard FPGA design tools.